This application claims the priority of Korean Patent Application No. 2002-40093, filed 10 Jul. 2002 in the Korean Intellectual Property Office, which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method of fabricating a non-volatile memory device, and more particularly, to a method of fabricating a non-volatile memory device having a structure of silicon-oxide-nitride-oxide-silicon (hereinafter, xe2x80x9cSONOSxe2x80x9d).
2. Description of the Related Art
Semiconductor memory devices, which are used to store data, are largely classified as volatile memory devices and non-volatile memory devices. When the supply of power is removed, data stored in a volatile memory device is lost, while data stored in a non-volatile memory device is maintained. Therefore, a non-volatile memory device is particularly applicable to use in various types of appliances that are not always connected to a power source, must operate at lower power levels, and experience frequent discontinuations of supplied power, for example mobile telephone systems and memory cards for storing music and/or image data.
In general, a cell transistor of a non-volatile memory device has a stacked gate structure in which a gate insulating layer, a floating gate electrode, an insulating layer, and a control gate electrode are sequentially formed on a channel region of the cell transistor. A non-volatile memory device with a SONOS structure includes a silicon layer in which a channel region is formed, an oxide layer for forming a tunneling layer, a nitride layer acting as a blocking layer, and a silicon layer acting as a control gate electrode.
FIG. 1 is a cross-sectional view of a conventional non-volatile memory device with a SONOS structure. Referring to FIG. 1, oxide-nitride-oxide layers 110 (hereinafter, xe2x80x98ONO layers 110xe2x80x99) are formed on a semiconductor substrate 100. The semiconductor substrate 100 includes high-density impurity-doped regions 102 that are used as source or drain regions. The ONO layer 110 is a stacked structure in which a first silicon oxide layer 112 operating as a tunneling layer, a silicon nitride layer 114 operating as a charge trapping layer, and a second silicon oxide layer 116 operating as a blocking layer, are sequentially deposited. A gate insulating layer 120 is formed on a portion of the semiconductor substrate 100 between adjacent ONO layers 110. Also, a control gate electrode 130 is formed on the ONO layers 110 and the gate insulating layer 120.
To program the non-volatile memory device of FIG. 1, a positive bias voltage is applied to the control gate electrode 130 and a suitable bias voltage is applied to the impurity-doped regions 102. Then, hot electrons in the semiconductor substrate 100 are trapped into a charge trapping region of the silicon nitride layer 114, which operates as a charge trapping layer, thereby changing the threshold voltage of the cell. To erase data stored in the non-volatile memory device of FIG. 1, a negative bias voltage is applied to the control gate electrode 130 and a suitable bias voltage is applied to the impurity-doped regions 102. Then, holes in the semiconductor substrate 100 are trapped into the charge trapping region of the silicon nitride layer 114 and recombined with extra electrons that exist in the charge trapping region, thereby changing the threshold voltage of the cell.
A conventional non-volatile memory device is fabricated such that the ONO layers 110 are formed on the semiconductor substrate 100, a gate insulating layer is formed between the ONO layers 110 on the semiconductor substrate 100, and the control gate layer 130 is formed over the resultant structure.
In such a conventional non-volatile memory device, electrical short-circuiting may occur at interfaces, i.e., portions A, between the silicon nitride layer 114, which is the charge trapping layer, and the control gate electrode 130. In this case, hot electrons, which were trapped in the silicon nitride layer 114 during the programming of the non-volatile memory device, may travel into the control gate electrode 130. While erasing data in the non-volatile memory device, electrons may move to the silicon nitride layer 114 via the control gate electrode 130.
The present invention provides a non-volatile memory device with a SONOS structure, in which the interface between the control gate electrode and the charge trapping layer provides for electrical insulation therebetween.
According to one aspect of the present invention, there is provided a method of fabricating a non-volatile memory device, the method including forming a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer on a semiconductor substrate; performing an oxidation process to form a silicon nitride oxide layer, as a blocking layer, at top and side surfaces of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and forming a control gate electrode on the silicon nitride oxide layer and the gate insulating layer.
Forming the silicon oxide layer and the silicon nitride layer pattern includes forming a silicon oxide layer on the semiconductor substrate; forming a silicon nitride layer on the silicon oxide layer; forming a photoresist layer pattern on the silicon nitride layer; performing an etching process on the resultant structure using the photoresist layer pattern as an etch mask so as to sequentially etch the silicon nitride layer and the silicon oxide layer, thereby exposing a portion of the semiconductor substrate; and removing the photoresist layer pattern.
Preferably, the silicon oxide layer is formed using a thermal oxidation process, the silicon nitride layer is formed using chemical vapor deposition (CVD), and the thickness of the silicon nitride layer is thicker than a desired thickness of the charge trapping layer.
Preferably, the oxidation process is a radical oxidation process. During the oxidation process, oxygen radicals may be generated using plasma or using high-temperature wet oxidation process. Preferably, the high-temperature wet oxidation process is performed at a temperature from 500xc2x0 C. to 1150xc2x0 C.